Add more ARM flag definitions and complete initialisation stage 1

diff --git a/arch/arm-head.S b/arch/arm-head.S
index ef9e8cd..1fe24ce 100644 (file)
--- a/arch/arm-head.S
+++ b/arch/arm-head.S
@@ -19,6 +19,7 @@
 
 #include <boot/linkage.h>
 #include <boot/version.h>
+#include <boot/arm.h>
 
     .section ".text", #alloc, #execinstr
 ENTRY(_start)
@@ -55,4 +56,8 @@ ENTRY(__init)
     bl      SET_SA                  @ sense amp settings
     bl      __cpu_early_init
 
+    msr     cpsr_c, #(USR_MODE | PSR_F_BIT | PSR_I_BIT | SVC26_MODE)
+    ldr     r0,=0x0050078
+    mcr     p15,0,r0,c1,c0,0      //; WCP15_SCTLR  r2
+    ISB                             @ macro for "isb sy" because compiler may not support opcode
 // EOF

diff --git a/include/boot/arm.h b/include/boot/arm.h
new file mode 100644 (file)
index 0000000..3c3127c
--- /dev/null
+++ b/include/boot/arm.h
@@ -0,0 +1,59 @@
+/*
+  ARM architecture bit flags and other definitions
+  Copyright (c) 2010 TJ <linux@tjworld.net>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program (See the COPYRIGHT file the base directory).
+    If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+  SOURCE: HTC Vision Linux kernel 2.6.32 source
+  SOURCE_FILE: arch/arm/include/asm/ptrace.h
+  SOURCE_URL: http://dl3.htc.com/RomCode/Source_and_Binaries/vision-2.6.32-g814e0a1.tar.gz
+  SOURCE_FOR: ARM bit flags
+*/
+
+/*
+  Program Status Register (PSR) bits
+  see ARMv7 Architecture Reference Manual, B1.4.2 "The special-purpose program status registers"
+*/
+
+#define USR26_MODE      0x00000000      // Interrupt Program Status Register
+#define FIQ26_MODE      0x00000001
+#define IRQ26_MODE      0x00000002
+#define SVC26_MODE      0x00000003
+#define USR_MODE        0x00000010      // Execution Program Status Register
+#define FIQ_MODE        0x00000011      //  ICI/IT bits
+#define IRQ_MODE        0x00000012
+#define SVC_MODE        0x00000013
+#define ABT_MODE        0x00000017
+#define UND_MODE        0x0000001b
+#define SYSTEM_MODE     0x0000001f
+#define MODE32_BIT      0x00000010
+#define MODE_MASK       0x0000001f
+#define PSR_T_BIT       0x00000020
+#define PSR_F_BIT       0x00000040
+#define PSR_I_BIT       0x00000080
+#define PSR_A_BIT       0x00000100
+#define PSR_E_BIT       0x00000200
+#define PSR_J_BIT       0x01000000
+#define PSR_Q_BIT       0x08000000      // Application Program Status Register
+#define PSR_V_BIT       0x10000000
+#define PSR_C_BIT       0x20000000
+#define PSR_Z_BIT       0x40000000
+#define PSR_N_BIT       0x80000000
+
+/* SOURCE_END */
+
+// EOF