Integrate arm-head.S and chipset-specific initialisation functions

diff --git a/arch/arch-init-7x30.S b/arch/arch-init-7x30.S
index 60c56ee..c2b0dd9 100644 (file)
--- a/arch/arch-init-7x30.S
+++ b/arch/arch-init-7x30.S
@@ -459,15 +459,15 @@ SYSI2:
 
         //; Make sure Link stack is initialized with branch and links to sequential addresses
         //; This aids in creating a predictable startup environment
-//;       BL      SEQ1
-//;SEQ1:  BL      SEQ2
-//;SEQ2:  BL      SEQ3
-//;SEQ3:  BL      SEQ4
-//;SEQ4:  BL      SEQ5
-//;SEQ5:  BL      SEQ6
-//;SEQ6:  BL      SEQ7
-//;SEQ7:  BL      SEQ8
-//;SEQ8:
+       BL      SEQ1
+SEQ1:  BL      SEQ2
+SEQ2:  BL      SEQ3
+SEQ3:  BL      SEQ4
+SEQ4:  BL      SEQ5
+SEQ5:  BL      SEQ6
+SEQ6:  BL      SEQ7
+SEQ7:  BL      SEQ8
+SEQ8:
 
         //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
         //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
@@ -686,8 +686,7 @@ SYSI2:
         FMXR  FPEXC, r1
 #endif *//* APPSBL_VFP_ENABLE */
 
-        /* we have no stack, so just tail-call into the SET_SA routine... */
-        b SET_SA
+        BX LR
 
 
 .ltorg

diff --git a/arch/arm-head.S b/arch/arm-head.S
index 12a6571..ef9e8cd 100644 (file)
--- a/arch/arm-head.S
+++ b/arch/arm-head.S
@@ -51,9 +51,8 @@ ENTRY(__init)
     bic     r0,r0,#0x0000B000       @ clear bit 10: Should Be Zero
     bic     r0,r0,#0x00000005       @ bit 2: data cache disabled. bit 0: MMU disable
     orr     r0,r0,#0x00000002       @ bit 1: strict alignment checks enabled
-    mcr     p15,0,r0,c1,c0          @write control register configuration
-    bl      SET_SA
+    mcr     p15,0,r0,c1,c0          @ write control register configuration
+    bl      SET_SA                  @ sense amp settings
+    bl      __cpu_early_init
 
-// when built binary image of arch-init-7x30.S should follow immediately
-    .align 1
 // EOF