.text
.code 32
-#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
-#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+#include <boot/arm-missing-opcodes.h>
/*
; LVT Ring Osc counter
#include <boot/linkage.h>
#include <boot/version.h>
#include <boot/arm.h>
+#include <boot/arm-missing-opcodes.h>
.section ".text", #alloc, #execinstr
ENTRY(_start)
--- /dev/null
+/*
+ ARM op-codes that compilers may not support
+ Copyright (c) 2010 TJ <linux@tjworld.net>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program (See the COPYRIGHT file the base directory).
+ If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __ARM_MISSING_OPCODES_H
+#define __ARM_MISSING_OPCODES_H
+/*
+ moved from arch/arch-init-7x30.S so other source can use them
+*/
+#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
+#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
+
+#endif