mrc p15,0,r0,c1,c0 @ read control register configuration data
bic r0,r0,#0x0000B000 @ clear bit 10: Should Be Zero
bic r0,r0,#0x00000005 @ bit 2: data cache disabled. bit 0: MMU disable
orr r0,r0,#0x00000002 @ bit 1: strict alignment checks enabled
mcr p15,0,r0,c1,c0 @write control register configuration
mrc p15,0,r0,c1,c0 @ read control register configuration data
bic r0,r0,#0x0000B000 @ clear bit 10: Should Be Zero
bic r0,r0,#0x00000005 @ bit 2: data cache disabled. bit 0: MMU disable
orr r0,r0,#0x00000002 @ bit 1: strict alignment checks enabled
mcr p15,0,r0,c1,c0 @write control register configuration