2 Initialise the Qualcomm MSM7x30 Processor
3 Copyright (c) 2010 TJ <linux@tjworld.net>
5 This program is free software: you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation, either version 3 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program (See the COPYRIGHT file the base directory).
17 If not, see <http://www.gnu.org/licenses/>.
20 #include <boot/linkage.h>
23 SOURCE: HTC Vision Linux kernel 2.6.32 source
24 SOURCE_FILE: arch/arm/mach-msm/arch-init-7x30.S
25 SOURCE_URL: http://dl3.htc.com/RomCode/Source_and_Binaries/vision-2.6.32-g814e0a1.tar.gz
26 SOURCE_FOR: MSM7x30 equates, status-codes, IOMEM addresses, CP15 functions
29 #define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
30 #define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
33 ; LVT Ring Osc counter
34 ; used to determine sense amp settings
35 ; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
37 .equ CLK_CTL_BASE, 0xA8600000
38 .equ A_GLBL_CLK_ENA, 0x0000
39 .equ A_PRPH_WEB_NS_REG,0x0080
40 .equ A_MSM_CLK_RINGOSC,0x00D0
41 .equ A_TCXO_CNT, 0x00D4
42 .equ A_TCXO_CNT_DONE, 0x00D8
43 .equ A_RINGOSC_CNT, 0x00DC
44 .equ A_MISC_CLK_CTL, 0x0108
45 .equ CLK_TEST, 0xA8600114
46 .equ SPSS_CSR_BASE, 0xAC100000
47 .equ A_SCRINGOSC, 0x0510
49 //;; Number of TCXO cycles to count ring oscillations
50 .equ TCXO_CNT_VAL, 0x100
53 .equ TCSR_CONF_FUSE_1, 0xAB600060 //; TCSR_CONF_FUSE_1 register
54 .equ TCSR_CONF_FUSE_4, 0xAB60006C //; TCSR_CONF_FUSE_4 register
56 //; SCORPION_L1_ACC (1:0) Fuses bit location
57 .equ L1_ACC_BIT_0, 12 //;12th bit of TCSR_CONF_FUSE_4
58 .equ L1_ACC_BIT_1, 13 //;13th bit of TCSR_CONF_FUSE_4
59 //; SCORPION_L2_ACC (2:0) Fuses bit location
60 .equ L2_ACC_BIT_0, 25 //;25th bit of TCSR_CONF_FUSE_1
61 .equ L2_ACC_BIT_1, 10 //;10th bit of TCSR_CONF_FUSE_4
62 .equ L2_ACC_BIT_2, 11 //;11th bit of TCSR_CONF_FUSE_4
64 //; CP15: PVR2F0 values according to SCORPION_L1_ACC (1:0)
65 .equ PVR2F0_00, 0x00000000
66 .equ PVR2F0_01, 0x04000000
67 .equ PVR2F0_10, 0x08000000
68 .equ PVR2F0_11, 0x0C000000
70 //; CP15: PVR2F1 values according to SCORPION_L1_ACC (1:0)
71 .equ PVR2F1_00, 0x00000008
72 .equ PVR2F1_01, 0x00000008
73 .equ PVR2F1_10, 0x00000208
74 .equ PVR2F1_11, 0x00000208
76 //; CP15: PVR0F2 values according to SCORPION_L1_ACC (1:0)
77 .equ PVR0F2_00, 0x00000000
78 .equ PVR0F2_01, 0x00000000
79 .equ PVR0F2_10, 0x00000200
80 .equ PVR0F2_11, 0x00000200
82 //; CP15: PVR0F0 values according to SCORPION_L1_ACC (1:0)
83 .equ PVR0F0_00, 0x7F000000
84 .equ PVR0F0_01, 0x7F000400
85 .equ PVR0F0_10, 0x7F000000
86 .equ PVR0F0_11, 0x7F000400
88 //; CP15: L2VR3F1 values according to SCORPION_L2_ACC (2:0)
89 .equ L2VR3F1_000, 0x00FFFF60
90 .equ L2VR3F1_001, 0x00FFFF40
91 .equ L2VR3F1_010, 0x00FFFC60
92 .equ L2VR3F1_011, 0x00FFFC40
93 .equ L2VR3F1_100, 0x00FCFF60
94 .equ L2VR3F1_101, 0x00FCFF40
95 .equ L2VR3F1_110, 0x00FCFC60
96 .equ L2VR3F1_111, 0x00FCFC40
100 .section ".start", #alloc, #execinstr
101 ENTRY(__init_msm_7x30)
103 ldr r1,=TCSR_CONF_FUSE_4